www.siliconstandard.com 1 of 5 p -channel enhancement-mode power mosfet low gate-charge bv dss -30v simple drive requirement r ds(on) 50mw fast switching i d -20a description the ssm9435h is in a to-252 package, which is widely used for commercial and industrial surface mount applications, and is well suited for low voltage applications such as dc/dc converters. the through-hole version, the ssm9435j in to-251, is available for low-footprint vertical g d s to-251 (j) g d s to-252 (h) g d s mounting. these devices are manufactured with an advanced process, providing improved on-resistance and switching performance. absolute maximum ratings symbol units v ds v v gs v i d @ t c =25c i d @ t c =100c i dm a p d @ t c =25c w/c t stg t j symbol value unit rthj-c thermal resistance junction-case max. 4 c/w rthj-a thermal resistance junction-ambient max. 110 c/w parameter rating drain-source voltage -30 gate-source voltage continuous drain current -20 a continuous drain current -13 a pulsed drain current 1 -72 operating junction temperature range -55 to 150 c linear derating factor 0.25 storage temperature range total power dissipation 31 w -55 to 150 c thermal data parameter 20 pb-free; rohs compliant. ssm 9 435 g h,j 2/16/2005 re v.2.1
www.siliconstandard.com 2 of 5 ssm9435gh,j 2/16/2005 re v.2.1 electrical characteristics @ t j =25c (unless otherwise specified) symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =-250ua -30 - - v d bv dss / d t j breakdown voltage temperature coefficient reference to 25c , i d =-1ma - -0.1 -v/c r ds(on) static drain-source on-resistance 2 v gs =-10v, i d =-10a - - 50 mw v gs =-4.5v, i d =-5a - - 90 mw v gs(th) gate threshold voltage v ds =v gs , i d =-250ua -1 - -3 v g fs forward transconductance v ds =-10v, i d =-10a - 9.6 - s i dss drain-source leakage current (t j =25 o c) v ds =-30v, v gs =0v - - -1 ua drain-source leakage current (t j =150 o c) v ds =-24v, v gs =0v - - -25 ua i gss gate-source leakage v gs = 20v - - 100 na q g total gate charge 2 i d =-10a - 10 16 nc q gs gate-source charge v ds =-24v - 3 - nc q gd gate-drain ("miller") charge v gs =-4.5v - 0.8 - nc t d(on) turn-on delay time 2 v ds =-15v - 9.6 - ns t r rise time i d =-10a - 18 - ns t d(off) turn-off delay time r g =3.3w , v gs =-10v - 19 - ns t f fall time r d =1.5w -14- ns c iss input capacitance v gs =0v - 463 740 pf c oss output capacitance v ds =-25v - 187 - pf c rss reverse transfer capacitance f=1.0mhz - 140 - pf source-drain diode symbol parameter test conditions min. typ. max. units v sd forward on voltage 2 i s =-10a, v gs =0v - - -1.2 v t rr reverse recovery time 2 i s =-10a, v gs =0v, - 34 - ns q rr reverse recovery charge di/dt=-100a/s - 30 - nc notes: 1.pulse width limited by maximum junction temperature. 2.pulse width < 300us , duty cycle < 2%.
www.siliconstandard.com 3 of 5 ssm 9 435 g h,j 2/16/2005 re v.2.1 fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance vs. gate voltage fig 4. normalized on-resistance vs. junction temperature fig5. forward characteristic of fig 6. gate threshold voltage vs. reverse diode junction temperature 0 20 40 60 80 024681 0 -v ds , drain-to-source voltage (v) -i d , drain current (a) t c =25 o c v g =-4.0v -4.5v -10v -8.0v -6.0v 0 10 20 30 40 50 60 70 02468 -v ds , drain-to-source voltage (v) -i d , drain current (a) t c =150 o c v g =-4.0v -4.5v -6.0v -10v -8.0v 0 1 2 3 -50 0 50 100 150 t j , junction temperature ( o c) -v gs(th) (v) 0 2 4 6 8 10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -v sd , source-to-drain voltage (v) -i s (a) t j =25 o c t j =150 o c 30 40 50 60 70 80 90 24681 01 2 -v gs , gate-to-source voltage (v) r ds(on) (m w ) i d =-10a t c =25c 0.6 0.8 1.0 1.2 1.4 1.6 -50 0 50 100 150 t j , junction temperature ( o c) normalized r ds(on) i d =-10a v g =-10v
www.siliconstandard.com 4 of 5 ssm 9 435 g h,j 2/16/2005 re v.2.1 fig 7. gate charge characteristics fig 8. typical capacitance characteristics fig 9. maximum safe operating area fig 10. effective transient thermal impedance fig 11. switching time waveform fig 12. gate charge waveform t d(on) t r t d(off) t f v ds v gs 10% 90% q v g -4.5v q gs q gd q g charge 100 1000 1 5 9 1 31 72 12 52 9 -v ds , drain-to-source voltage (v) c (pf) f =1.0mhz c iss c oss c rss 0.01 0.1 1 0.00001 0.0001 0.001 0.01 0.1 1 t , pulse width (s) normalized thermal response (r thjc ) p dm duty factor = t/t peak t j = p dm x r thjc + t c t t 0.02 0.01 0.05 0.1 0.2 duty=0.5 single pulse 0.1 1 10 100 0.1 1 10 100 -v ds , drain-to-source voltage (v) -i d (a) 1ms 10ms 100ms 1s dc t c =25 o c single pulse 0 2 4 6 8 10 12 0 5 10 15 20 25 30 q g , total gate charge (nc) -v gs , gate to source voltage (v) i d =-10a v ds =-24v
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